Decoupling High Speed Logic

This is in response to enquiry from Chris Halford <Chris.Halford@3Dlabs.com> about how to decouple digital logic.

I have already written three emails. Here, I shall go further with the analysis. This goes much further than anyone has ever gone before, and will be extremely difficult to understand, particularly in the absence of pictures/diagrams. However, the ideas need to be documented.

Decoupling high speed logic.

When digital logic systems comprising circuits using a 5 volt supply are used, the designer tries to safeguard the integrity of the 5v supply. That is, he tries to ensure that the voltage difference between the 0v pin and the 5v pin on a chip is kept close to 5v. To this end, he attaches an array of (decoupling) capacitors judiciously spaced. More capacitors cost more money and waste space. Less capacitors fail to hold up the local 5v level well enough.

Let us consider logic circuits which I used in 1964. The NOR or NAND logic gates had a propagation delay of 1.35nsec. Output signal rise time into 50 ohms was 2nsec.

We will consider the case when a logic gate is connected to a 1uF decoupling capacitor three inches away by two parallel printed lines, 0v and 5v, the characteristic impedance between the lines being a reasonable 40 ohms. We will consider only the proposed increase in electric current demanded by the logic gate from 5v for dumping into 0v when it switches. Let us suggest that that increased current is 100ma. Initially, this current has to be supplied by the (energy) current/charge resident between the two lines three inches long.

For the next step, it is necessary to grasp the Contrapuntal, or Catt, model for a charged capacitor, the charged capacitor being the 3 inch pair of wires from logic gate to decoupling capacitor.

According to this model, a steady charged capacitor is not steady at all. It contains energy current (=TEM Wave) vacillating from end to end of the capacitor at the speed of light. At any instant, a two and a half volt signal is travelling to the left, and a two and a half volt signal is travelling to the right. At each end of the 3 inches (if the capacitor were absent) the energy current would fully reflect. With the capacitor present the picture is more complicated. However, the system, of 3in transmission line and capacitor (which is a low impedance transmission line) has settled down, with energy current vacillating from end to end of the 3 inches, and energy current vacillating from end to end of the capacitor. Each time energy current arrives at the junction between 3 inches and the capacitor, some of it reflects, and some of it leaks into the other circuit. (A circuit is either the three inches, or the capacitor.) A state of dynamic equilibrium has been reached, due to losses. That is, a pulse could not vacillate from end to the of the three inches because of resistive losses, unless the length of the pulse is exactly six inches, and it is chasing its own tail, thus leading to zero resistive loss due to electric current in the wires, because the electric currents in the two directions cancel out. Leakage current and leakage losses through the epoxy glass are legligible.

At any moment, two and a half volts of energy current are presenting themselves to the logic gate, to be rebuffed (by an open circuit, or at least by a very high input impedance presented by the logic gate between its 0v and 5v pins to any would-be increase in current. However, when the logic gate begins to switch, and begins to want to conduct a further 10ma between its 5v pin and its 0v pin, the input impedance which it presents to the pair of lines, 5v and 0v, falls. It falls just enough to enable it to take the first little rise in its internal current. Note that the logic gate’s output rise time is 2nsec, so we will assume the 10ma internal rise will take place over 2nsec. In an epoxy glass board, a signal travelling between two embedded printed wires travels 6 inches in a nsec. During the first nsec, when there has been insufficient time for the decoupling capacitor to be brought into the new situation, because the round trip down 3 inches to capacitor and 3 inches back from capacitor takes 1 nsec, the logic gate has to be satisfied with the two and a half volt incident energy current arriving down a transmission line with a Zo of 40 ohms. However, with an output rise time of 2nsec, it should, after the duration of 1nsec, have taken in half of the extra 10ma. To ge this from an incident two and a half volts coming in with a source impedance of 40 ohms, it is necessary for the nominal 5v supply at the logic gate to drop by 0.2v (v=iR=40ohms x 5ma) . Thus, after the first nanosecond, the increased internal current in the logic gate, which has reached 5ma, will have caused the nominal 5v local supply to drop by 0.2v .

However, since this operation, of dumping charge/current into the output line will cause a drop in the 5v supply, there will also be a drop in the 5v supplied to the standing circuits in the logic gate. A drop in the 5v causes a disproportionate drop in the amount of current taken by a logic gate in its normal functioning. Thus, the logic gate will be able to steal some of its standing working current to use to bolster the output signal. This will be satisfactory so long as the drop in 5v supply to the circuit is not so great as to cause circuit malfunction. This would be much more serious in a bistable than in a logic gate, which would merely become “spongy”, like a car braking system with air in it.

After the first 1nsec, the reaction of the 1uF decoupling capacitor has to be considered.

For this, we have to first study a somewhat similar situation, the L-C oscillator http://www.ivorcatt.com/4_5.htm . A full grasp of that may give us a good start into our present problem, which is that of a C-C system, one C being three inches, the other being the 1uF capacitor.

To be continued. Ivor Catt 15may03

We will again consider the case when a logic gate is connected to a 1uF decoupling capacitor three inches away by two parallel printed lines, 0v and 5v, the characteristic impedance between the lines being a reasonable 40 ohms. We will now consider only the charge/current required by the switching logic gate to drive its output pin, which is connected to a two wire transmission line (signal line and 0v line) with a characteristic impedance of 50 ohms between them (as a two wire system). From the point of view of the logic gate, it takes charge/current out of its 5v input pin and dumps the same amount of charge/current into its 0v pin, and thence to the decoupling capacitor.

At any moment, two and a half volts of energy current are presenting themselves to the logic gate, to be rebuffed (by an open circuit, or at least by a very high input impedance presented by the logic gate between its 0v and 5v pins to any would-be increase in current. However, when the logic gate begins to switch, and begins to want to deliver a 5v pulse between its output pin and its 0v pin, the input impedance which it presents to the pair of lines, 5v and 0v, falls. It falls just enough to enable it to deliver the first little rise in its output. Note that the logic gate’s output rise time is 2nsec. In an epoxy glass board, a signal travelling between two embedded printed wires travels 6 inches in a nsec. During the first nsec, when there has been insufficient time for the decoupling capacitor to be brought into the new situation, because the round trip down 3 inches to capacitor and 3 inches back from capacitor takes 1 nsec, the logic gate has to be satisfied with the two and a half volt incident energy current arriving down a transmission line with a Zo of 40 ohms. Since the Zo of its output transmission line is 50 ohms, it can therefore deliver 50/90ths of the two and a half volts into its output; roughly one and a half volts. However, with an output rise time of 2nsec, it should, after the duration of 1nsec, have delivered one half of the 5v output, or two and a half volts. Thus, if the decoupling capacitor is three inches away, the logic gate’s output will only rise a quarter of the way rather than half way after the first nanosecond.

After the first nsec, the reaction of the 1uF decoupling capacitor has to be considered.

To be continued. Ivor Catt 15may03

Ivor Catt 17may03

The writing of 15may03, above, gets stuck in the sand. In summary, let us say that after the first nxec, the 1uF capacitor will cause the 5v supply at the logic gate to be held up better than in the first 1nsec. Note that even before the gate switched, there was a dance of energy along all the pairs of 5v and 0v lines between one capacitor and another. When the logic gate switches, so demanding an increase in current, more of the energy (current) travelling towards it gets used by the gate rather than merely reflecting back to where it came from, be it another pair of 5v and 0v lines, or another 1uF capacitor.

This time, 17may03, we will take another approach. Consider a large printed curcuit board with a square grid of 5v lines close to a square grid of 0v lines, the pitch (=length of a square’s side) being 3 inches. If a logic gate switches half way between two of the 5v-0v corners, then for the first half a nanosecond the extra (energy) current is supplied by the two short stubs of transmission line, each with a source impedance of 40 ohms. Thus, the extra 5v current is delivered with the disadvantage of a 20v source impoedance, leading to a small drop in the 5v supply at the logic gate. After the first half nanosecond, the energy current is being supplied from three three inch pairs in parallel, which is what exists at the far end of each one and a half inch length. These three in parallel, plus the other three in parallel, have a source impedance of one sixth of 40 ohms, i.e. about 7 ohms. Thus, provided only one logic gate switches at that moment, the 5v supply is very good even if there are no 1uF decoupljng capacitors. Note, by the way, that since we will never know h9ow many logic gates switched at the same moment, it is very unwise to decide whether the system is sound on the basis of test runs. The only viable way is by calculation.

At this point, I trust you will have seen that the purpose served by the judiciously distributed 1uF capacitors is to prevent superposition of switching problems from more than one switching logic gate. The decision on how close to space 1uF capacitors should be driven by the fear that many circuits will switch at the same time in the section between a pair of 1uF capacitors.

All of this analysis surely indicates the total irrelevance of “resonant frequency”. In a mechanical system we understand full well that resistive damping prevents resonance. In our case, the sight of the near end of a 40ohm transmission lines is much like seeing some friction in a mechanical system, or a resistor in an oscillatory circuit. Our system, looked at from that point of view, is extremely heavily damped by the array of transmission lines which it contains. Also, any sudden increase in demand for current causes “ripples” to travel out from that point to more and more 5v and 0v buses and more and more 1uF capacitors. The problem is just not amenable to analysis on the basis of frequency. Rather, the problem is one of catastrophe, when a sudden demand for more current is made, and this has to be supplied, more or less, from that moment and for ever afterwards.

The Good Neighbour Policy.

This was discussed by Walton in a Wireless World article in the 1980s. When the 5v supply begins to collapse at a point, every digital circuit responds by taking much less electric current out of the 5v than heretofore. Since mose of the drops from 5v to 0v are (fixed) diode drops and not resistive, we find that a drop of 10% in the 5v supply leads, not to a 20% drop in current demand from a circuit using the 5v supply, as it would if it were a resistive demand, but rather a 40% drop, since half of the drops within the circuit are fixed 0.7v diode drops.

Ivor Catt 17may03